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Processor Architecture Quiz

7 medium multiple-choice questions about von Neumann, Harvard, and contemporary processor architectures from the provided video.

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Drussy
Published August 14, 2026

Quiz Questions & Answers

Review every prompt, the correct responses, and helpful context to prep for your own run-through.

Question 1: In the classic von Neumann architecture, what is a defining feature of how instructions and data are stored?

Instructions are on separate read-only chips

Each instruction uses a dedicated memory bus

Data is stored in multiple distributed nodes by default

They share a single memory space and format

Question 2: How does Harvard architecture differ from von Neumann in memory organization?

It requires a single register file for both instructions and data

It eliminates the need for a control unit entirely

It uses separate memory units and buses for instructions and data

It merges multiple instruction sets into one shared cache

Question 3: Which architecture type is most associated with performing one instruction at a time via a linear fetch-decode-execute cycle?

Von Neumann

SIMD

Distributed computing

MIMD

Question 4: If a GPU applies one operation simultaneously to many pixels, which contemporary architecture concept from the video best describes that behavior?

Von Neumann sequential processing

SIMD (single instruction, multiple data)

Single-core serial execution

Harvard dual-bus fetching

Question 5: Which contemporary model describes different cores executing different instructions on different data items?

MIMD (multiple instruction, multiple data)

Von Neumann pipeline

SIMD streaming

Harvard architecture

Question 6: How does distributed computing, as described in the video, extend processor architecture concepts?

A single CPU emulates many cores by time-slicing

Multiple separate computers on a network share parts of a larger problem

Instructions and data are permanently fused into one memory

GPUs are repurposed as general-purpose von Neumann CPUs

Question 7: Which statement best captures why contemporary architectures differ from a pure von Neumann design?

They introduce parallelism and memory or execution models beyond a single sequential fetch-execute stream

They mandate a single instruction set across all devices on a network

They always revert to Harvard-style separate memory for every component

They remove registers entirely to simplify access